PHOTONICSENSE · LIVE FROM
NDR (Jul 2026) · Q2 FY27 deck + AWS expansion folded (26–27 Aug)
Where the Memory Goes
NVIDIA just reorganised its own demand for investors: Hyperscale · AI Clouds, Industrial & Enterprise (ACIE) · Edge — and declared visibility to $1T+ of cumulative Blackwell + Rubin revenue through CY2027. Every dollar of that is a system with our memory in it. This page re-reads their reorganisation from one layer down: the same three buckets, mapped to the bits SK Hynix sells into each. Their demand slide is our order book. And the reframe this page exists to prove: SK Hynix is a play on AI memory-bandwidth demand itself — not a derivative NVIDIA trade. Rubin needs it, Jalapeño needs it, TPU and Trainium need it; the accelerator war multiplies HBM buyers rather than replacing them. Two voices logged 3 Sep: Gavin Baker — don’t watch token prices; if OpenAI loses share to open-source, Grok or Muse, infrastructure demand can still accelerate (memory demand is not one-company-dependent); Beth Kindig — agentic AI at ~84% of workloads and ~101 quadrillion monthly tokens by 2030, ~18× May’s total. Added 5 Sep: hyperscalers building behind-the-meter power and selling surplus back (Baker) — the "grid is full" worry weakens; AMD + Cisco + HUMAIN up to 250MW from 2027 (Kindig); discrete GPU sales at a four-year high despite memory prices; high-end Macs for local AI short, buyers switching to NVIDIA — DRAM and HBM demand, both ours.
As of 5 Sep 2026
000660 ₩1,647K close 4 Sep (+3.2%, share print absorbed, foreigners #1 buyer) · tape: 1.693 → ~1.613 → 1.596 → 1.647
52w ₩253K – ₩2,987K
Consensus PT ₩3.16M · 39 analysts · Strong Buy
Next earnings Oct 27
Blackwell + Rubin visibility
~$1.2T
$1T (NDR) + ~$200B implied by the FY28 guide (+70% → ~$691B)
ACIE growth (Q2 FY27)
+138%
vs hyperscale +101% YoY · crossover in 2–6 quarters at current pace
Tokens / month
123T
Apr 2026, OpenRouter · 21T in Jan 2025
NVIDIA FCF FY26
$97B
$49B in Q1 FY27 alone · funds supply prepayments
THE SIMPLE VERSION
AI chips need memory, and each new chip needs more of it. NVIDIA’s growth (+70% guided), a fourth mega-buyer (SpaceX), Korea’s sovereign build, custom ASICs (every one an HBM socket) and, later, robot fleets all land on SK’s product — so the chain grows
faster than the customer. Nothing in silicon reduces memory demand; the candidates shift where it sits or who earns the premium, and SK supplies every form (see the Disruption Register). The bet is growth versus the street’s plateau.
The demand engine, in NVIDIA's own numbers
Data centre revenue by NVIDIA's new segmentation — the machine that converts capex into HBM orders. Q2 FY27 (quarterly deck, 26 Aug): revenue $96.2B, +106% YoY, growth accelerating a 4th consecutive quarter; hyperscale $48.7B / ACIE $40.3B; GM 75.0% (+2.6pts YoY); Q3 guide $108B at 74.0% GM — with zero China DC compute assumed. And the line that matters most: Vera Rubin production shipments commenced early August — "CPU, LPX, and STX are new growth drivers". HBM4 revenue recognition is now live, not pending.
NDR Jul 2026 (sell-in, $B). Totals incl. edge: 61 / 130 / 216 / 82.
Cumulative Blackwell+Rubin revenue visibility. New since GTC DC 2025: Anthropic, Gemini, XAI, MetaSL, multiple OSS labs.
The read for us: the customer doubled its declared multi-year envelope in nine months, then broke its own guidance cadence at Q2 to guide FY28 at +70% (~$691B vs $570B consensus) — analysts read that as ~$200B added to the $1T. HBM is reported at >50% of AI accelerator BOM, Morgan Stanley named memory first among delivery constraints — and the Q2 call confirmed it from the other side: NVIDIA held margins "in the face of memory cost headwinds" while Reuters reports +15% server price rises. Our ASPs are now a visible line in the customer's P&L, being passed through, and absorbed. That is pricing power observed, not asserted.
Why the curve keeps rising — tokens and old silicon
Two of NVIDIA's proof points, both memory stories underneath.
OpenRouter via NDR. Inference is memory-bound: the KV cache lives in HBM.
SemiAnalysis via NDR. Cloud rental pricing on 2- and 5-year-old GPUs, trailing change.
Token generation is up ~6× in fifteen months and now profitable — NVIDIA's phrase is "useful AI has arrived" (GitHub: 1.4B commits, 90M PRs merged, ~$9T of effective developer productivity). Meanwhile five-year-old A100s are appreciating and H100 rents rose 21% in six months: compute scarcity extending useful life. For memory that's demand at both ends — new HBM4 builds and a retained HBM3E fleet that never frees up supply. Scale check: Goldman's total-processing lens (a different universe to OpenRouter's router subset) puts the current run rate at ~11 quadrillion tokens/month — already ~2× Goldman's own May-2026 estimate — heading for 47Q by 2028 and ~120Q by 2030, with agentic workloads ~84% of it. Demand is outrunning the forecasters who model it.
Revenue per gigawatt — and memory's share of it
The most translatable number on the Q2 call. Jensen mapped the ladder himself: Hopper ~$18B/GW → Grace Blackwell ~$25B/GW → Vera Rubin ~$40B/GW. Power is the binding constraint, so revenue density per GW is the game — and memory density is what buys it.
System $/GW: NVIDIA Q2 FY27 call. Memory-content band: our est. at 25–35% of system value (HBM + LPDDR/SOCAMM + storage attach), midpoint shown — assumption visible, true-up as Rubin BOMs disclose.
The translation: tokens-per-watt is NVIDIA's KPI, and the physical lever underneath it is HBM bandwidth per watt — which is why memory content per GW more than doubles Hopper→Rubin while CoreWeave measures Rubin at ~10× tokens/MW vs GB200 (800K vs 80K TPS/MW on DeepSeek R1). Run the arithmetic forward: FY28 guide ~$691B at ~$40B/GW ≈ ~17GW of systems in one year; at a 25–35% memory share that is roughly $170–240B of memory content through NVIDIA systems alone — before hyperscaler ASICs (also HBM sockets), general-server DDR5, mobile, and storage. That is the demand-side ceiling check under the settled ₩800T FY27 chain: aggressive, and now the customer's own guidance is walking toward it.
The industries using memory — NVIDIA's buckets, our bits
NVIDIA's three demand segments, restated as memory end-markets. Shares are our 2026E structure (est.) of SK Hynix revenue — estimates, marked as such, to be trued against Q3 disclosure (Oct 27).
GPU fleets and internal silicon — every serious hyperscaler ASIC (TPU, Trainium, MTIA) is an HBM socket too. We sell into whichever chip wins the workload. Plus the invisible half: server DDR5, where MS counts memory at up to ~73% of server BOM, and AI eSSD (Solidigm) underneath it all.
Named by NVIDIA: Amazon · Google · Meta · Microsoft · OCI · SpaceXAI — plus their in-house accelerators, which NVIDIA doesn't count but we ship into. Now with a named mechanism: NVLink Fusion + NVHBM gives Trainium NVIDIA's custom HBM "in partnership with memory suppliers" (AWS PR, 26 Aug) — the ASIC lane just standardised on the memory we make.
AI Clouds, Industrial & Enterprise
~25% est.
NVIDIA's fastest-growing bucket — $40.3B in Q2 FY27, +138.5% YoY (vs hyperscale +101%), with sovereign + neoclouds +35% QoQ and tripled YoY. Management: about half the business, "growing 100% a year". On current pace ACIE overtakes hyperscale within 2–6 quarters. Every NVL72 that lands here carries the same HBM4 + LPDDR (SOCAMM on Vera) + storage stack, but with more buyers and less monopsony risk.
Named by NVIDIA: Anthropic · OpenAI · Cursor · Perplexity · SSI · Baseten · Tesla · TSMC · Foxconn · Lilly · Jane Street · CVS — demand breadth we could not have claimed a year ago.
Edge & Physical AI
~20% est.
Phones, AI PCs, cars, robots. NVIDIA frames physical AI as a $50 trillion end market — and every robot, AV and edge box is LPDDR5X + GDDR7 + NAND, not HBM. This is where our LPDDR leadership and mobile/client franchise stops being "the legacy business" and becomes the physical-AI attach layer.
Carriers: smartphones (LPDDR5X) · AI PCs (LPDDR/DDR5) · automotive & robotics (LPDDR, GDDR7, UFS/eSSD) · Jetson Thor-class edge systems — now incl. Amazon Robotics on the Jetson/Isaac/Omniverse stack (26 Aug).
Structure est. from product mix + industry data (TrendForce-class splits); explicitly an estimate, not disclosure. True-up scheduled at Q3 results.
Product × industry — every lane we sell into
The full matrix. ● core demand · ◐ growing attach · — not a lane. One honest hole flagged in red text below.
| SK product | Hyperscale AI | ACIE | Edge / Physical | What changed in the NDR |
|---|
| HBM3E / HBM4 | ● | ● | — | ~70% of NVIDIA's HBM4 allocation; one-year cadence locked to Rubin → Rubin Ultra |
| Server DDR5 / RDIMM | ● | ● | — | Every AI server still ships TBs of DDR5; the quiet second engine of the supercycle |
| LPDDR5X / SOCAMM | ◐ | ◐ | ● | Vera CPU pools LPDDR with HBM4 over NVLink-C2C — and SOCAMM2 192GB mass production has begun (1c-nm LPDDR5X for Vera Rubin; 2× bandwidth, ~75% better power vs RDIMM). The attach leg is shipping. A third demand leg on the horizon (not modelled): physical AI — Musk’s G20 "billion humanoids in ten years" is a speculative upside scenario, but the robot-fleet training/simulation infrastructure that precedes it is HBM and server-DRAM, and it arrives first. Sovereign compute in the home market: Korea’s $919B programme targets 8.4GW by 2029 and 18.4GW by 2035 (SK Group 5GW phase 1 + 10GW phase 2; 2GW of Rubin committed; three sites totalling 4.4GW already active per SemiAnalysis) — Vera Rubin on HBM4, ours. A fourth custom socket joins: Qualcomm HBC near-memory architecture — Samsung + SK hynix confirmed collaborators, ship 2027, Meta-first server CPU late 2028. |
| GDDR7 | — | ◐ | ● | GeForce RTX + edge inference; note Rubin CPX (GDDR7) quietly left the roadmap — see LPU flag |
| eSSD / NAND (Solidigm) | ● | ● | ◐ | BlueField-4 STX storage tray in every rack diagram; storage named an incremental growth pillar |
| HBF (2027+) | ◐ | ◐ | — | High Bandwidth Flash (co-developed with Sandisk) extends the HBM↔LPDDR↔NAND tiering we sit inside at every layer |
The one bucket that doesn't buy from us: Groq LPX racks (LP30, 512MB on-die SRAM, Samsung 4nm, 256 chips/rack, full production since 24 Aug). Held at the existing −2–5% bear sizing — the roadmap casualty was CPX/GDDR7, not HBM, and AFD keeps prefill + KV cache on HBM GPUs. Tripwires below.
The customer's roadmap is a memory roadmap
One-year cadence, memory named at every generation. The 2028 line is the structural shift.
2024–25 · SHIPPING
Blackwell / Ultra
HBM3E
Demand so strong it pushed our HBM4 line conversion Q2→Q3 2026. The cash cow funding the transition.
2026 · SHIPPING SINCE EARLY AUG
Rubin (NVL72)
HBM4
~70% allocation ours — and production shipments have commenced (Q2 deck). Base die on TSMC logic; MR-MUF carries through. 8-hi mix rising in H2 — ASP-mix watch item.
2027 · ROADMAP
Rubin Ultra
HBM4E
The scarcity point — hybrid bonding won't be ready (Hot Chips, Aug 23), so supply is physics-capped. Pricing power into the peak window.
2028 · ROADMAP — PULLED FORWARD
Feynman
Die-Stacking CUSTOM HBM
Custom HBM is no longer waiting for 2028. It has a product name — NVHBM — and its first third-party socket: Trainium, via NVLink Fusion, "in partnership with memory suppliers" (AWS, 26 Aug). Co-designed memory arrived two years early, and it's being licensed outward.
Their envelope, our chain
SK Hynix revenue — the live Command Deck chain (₩T), identical to index.html — against the demand context above. Clean EPS (one-offs stripped, new-fab D&A charged) on the orange line.
Live chain: FY26 ₩359T (clean EPS ₩270K) → FY27 ₩816T (₩583K) → FY28 ₩1,102T (₩753K); engine outputs: 12-mo blended E[V] ₩3.92M (all-branch mean, 44–45% bear mass carried) · flood-fan median ₩5.12M (v9.2, 12 Aug; ≥2× at 66% post-recal; p5 ₩2.15M) · year-end path (Patel trim reversed 28 Aug on evidence): ₩5.5M · 8.0 · 8.4 · 7.9 pause · 8.5. Growth check vs the customer: the chain grows ×2.27 in 2027 (bits +24%, weighted price +79%) against NVIDIA’s +70% FY28 guide — much faster than the customer — and then only +35% in 2028, the model’s own deceleration, because memory content per chip rises through the roadmap (192GB HBM3E → 288GB HBM4 → HBM4E; $18B → $25B → $40B per GW on Jensen’s ladder), HBM4 carries an ASP premium, evicted commodity DRAM reprices, and new attach legs (SOCAMM, NVHBM) stack on top. The constraint is wafers, not orders — excess demand is captured through price and mix, which is why the margin printed 76%. What the chain already includes vs what it deliberately does not (28 Aug register): Included — Q3/Q4 contract reprice (+20%), the HBM4-over-HBM3E ASP premium, 8-hi→12-hi mix, eviction-driven conventional-DRAM repricing, and volume at the M15X/M17 ramp schedule; the proof it is price×volume and not volume-only: FY26 needs H2 ₩228T against H1’s banked ₩132T (+73% half-on-half — that is price doing work), FY27 grows far faster than the customer (×2.27 vs +70%), and the 76% Q2 operating margin is price growth made visible. Not yet in the numbers, on purpose — the 26-28 Aug wave (NVDA’s larger FY28 base, SpaceX ~10GW outside the top-5, AWS’s 2M GPUs, the $40B/GW Rubin ladder, SOCAMM2 attach), the shortage-through-2030 statement (held at the 2029-pause review), and 2027+ HBM4E pricing under the no-cap regime. One challenge checked against the pricing line (2 Sep): SemiAnalysis’s estimate that NVIDIA secured favorable HBM pricing, and UBS’s "may cap near-term upside," were weighed against the record — SK hynix’s LTAs are floors without ceilings (TrendForce; Q2 call: pricing "responds to volatility," typically five years, with deposits), and Q2 DRAM ASP printed +30% under them. Primary source wins; the Q3 ASP print is the arbiter — and July’s realised export data (HBM unit value $76.13, +9.5% MoM; DRAM +24.3%; volumes down, values up) says pass-through is working, while spot HBM at ~5× contract levels says the upside register is real if the formulas track spot. TAM cross-check (corrected 5 Sep): FY27 ₩816T ≈ $600B needs ~45–47% of the street’s $1.3T memory TAM against SK’s ~40% blended share — price and share must deliver; FY28 ₩1,102T needs the TAM near $2.0T. The whole chain sits above the street’s path; FY27 is the first test (Oct 27, then January). Each has a quantification date: the chain re-derives on Q3 actuals, Oct 27 — the first print containing HBM4 volume at repriced contracts — and the 2029 multiple moves only on its armed triggers. Until then the stated skew stands: the demand inputs sit above the chain’s assumptions, not inside them — upside risk, named and dated, not averaged in early.. Q2 actuals: revenue ₩79.32T, OP ₩60.54T at a 76% margin; reported EPS ₩131.5K includes the ~₩63.3T Kioxia one-off — clean EPS is the tracking metric. Shareholder returns: the ₩40T buyback (~24.07M shares, 3.3%, all cancelled) is running ~1.7× ahead of schedule; net cash prints ₩69.4T — the old "₩100T gate" framing stays retired per the 17 Aug correction. NVIDIA counterparty strength ($97B FCF FY26, $21.3B in Q2 alone, capital return ~$26B/qtr while prepaying supply) de-risks the ₩54T Yongin Y2 + Cheongju M17 commit — and 2027 industry supply is already contracted ("no room for new buyers", 4 Aug).
Signals folded in · falsifiers attached
House rule: every claim on this page carries the condition that would kill it.
GREEN
ACIE ≈ 50% of DC revenue and outgrowing hyperscale NDR Jul 2026
Demand breadth is the anti-fragility upgrade: a hyperscaler capex pause no longer maps 1:1 onto HBM orders.
Falsifier: ACIE share falls below 40% for two consecutive quarters, or a hyperscaler capex cut coincides with an SK order cut.
GREEN
Token curve exponential and now profitable OpenRouter / GitHub via NDR
Profitable tokens = data-centre operators expand compute = memory pull. Inference (KV cache) is HBM-resident.
Falsifier: tokens/month growth <10% QoQ for two quarters, or GPU cloud pricing turns negative 6-mo trailing.
GREEN
Custom HBM on the official 2028 roadmap Feynman · NDR Jul 2026
Commodity → co-designed silicon. Deepens incumbent lock-in and margin structure at exactly the point bears expect mean reversion.
Falsifier: a Samsung custom-HBM program win on Feynman-class silicon → immediate bear-file escalation.
AMBER
LPU decode layer made permanent LP30 → LP35 (Rubin Ultra) → LP40 (Feynman)
SRAM decode is now a roadmap line, not an experiment — the Q2 deck names LPX a "new growth driver" alongside CPU and STX — and Samsung is the foundry (relationship halo). Casualty so far: GDDR7/CPX, not HBM. Sizing held at −2–5%.
Tripwires: LPX attach >1 rack per NVL72 in disclosed builds · LP-series takes prefill/attention work · SK LPDDR mix guided up at HBM's expense.
GREEN
NVHBM — custom HBM arrives two years early, and points outward AWS–NVIDIA expansion · 26 Aug
NVIDIA productised custom high-bandwidth memory as NVHBM and is extending it via NVLink Fusion to Trainium — Annapurna gets "faster, more power-efficient memory… in partnership with memory suppliers". Read it twice: the hyperscaler-ASIC lane, the one the bears said would escape us, just standardised on an NVIDIA memory spec that we manufacture. The Feynman thesis pulled forward from 2028 to now, with the custom-HBM TAM extended beyond NVIDIA's own GPUs. The tension: NVIDIA owning the spec makes dual-sourcing inside the standard easier — margin-capture and Samsung-qualification watch, not a demand watch.
Tripwires: Samsung named an NVHBM launch supplier ahead of us · NVHBM licensing terms that compress supplier margin vs standard HBM4 · a second ASIC (TPU/MTIA) adopting NVHBM = TAM expansion, log as GREEN.
GREEN
AWS alone: 2M more GPUs in 2027–28, on top of 1M+ already committed AWS–NVIDIA · 26 Aug
Blackwell Ultra, Rubin and Rubin Ultra — Rubin-class parts carry ~8 HBM4 stacks each, so 2M GPUs is on the order of ~16M incremental HBM stacks from one customer's expansion (est., mix-dependent). Plus 100K GPUs for US federal IL6+ AI factories (the sovereign bucket crystallising), Vera CPUs on AWS (LPDDR/SOCAMM attach beyond NVIDIA's own racks), and Amazon Robotics adopting the physical-AI stack (edge bucket). Huang's framing: demand is "running ahead of every forecast". One press release, five of our demand buckets.
Falsifier: AWS trims or defers the 2M commitment, or Trainium share of AWS AI capacity rises while the NVIDIA fleet target falls.
GREEN
Capex wall confirmed above consensus Kress, Q2 FY27 call · 26 Aug
Cloud industry backlog >$2T; top-5 hyperscaler capex ~$800B in 2026 → $1.3T in 2027 — ~$200B (18%) above consensus, from the counterparty with the best demand visibility on earth. Big-4 deploying $432B in 2H26 alone. And the wall is taller than the number: SpaceX targets ~10GW in 2027 (~$300–500B capex, SemiAnalysis) — outside the top-5 figure entirely, NVIDIA-exclusive, while Microsoft has signed 10GW of binding commitments YTD (~$300B). US Census data-centre construction spending ran above $75B annualised in July (~+60% YoY) and Microsoft’s fiscal-year capex reached ~$145B (per the 2 Sep watch note). Scale check in bytes: 10GW at NVL72-class density ≈ 70,000 racks ≈ 5.1M GPUs ≈ ~1.5 exabytes of HBM (illustrative — GB300 density; 2027 skews Rubin, which carries more memory per package). And the scarcity window is now bracketed by the principals themselves: the buyer (NVIDIA) warns shortages could persist through 2028; the biggest supplier’s CEO says on the record "until the end of 2030"; Micron guides a 50% demand-supply gap with no meaningful capacity before 2028; TechInsights (independent, FT 4 Sep): pricing +200% YoY, no greenfield until ~2028. Google (SEMICON Taiwan): high-performance memory is now more than 75% of an AI server’s hardware BOM and workloads are shifting from compute-bound to memory-bound. And the contracts themselves are going long: industry tenor shifting from one-year to 3-5-year commitments, with NVIDIA reportedly signing multi-year DRAM + HBM agreements with SK and Micron (Edgewater) — buyers contracting straight through the window the bear case reserves for oversupply. HBM now consumes 23% of DRAM wafer output at one-third the GB per wafer of DDR. Cross-check: Baker's HBM = 30–40% of hyperscaler capex by 2027 → the arithmetic now implies an HBM TAM far above our old anchor (see supersession flag below).
Falsifier: any top-5 hyperscaler guides 2027 capex down QoQ, or the $1.3T is walked back within two quarters.
GREEN
Memory named as NVIDIA's cost headwind — absorbed, then passed through Q2 FY27 call / Reuters
Q2 GM printed 75.0%, up 2.6pts YoY, while absorbing memory cost headwinds; Q3 guided to 74.0% — a ~100bp bite, below our 200bp tripwire — while server prices reportedly rise +15%. Our ASPs are visible in the buyer's P&L and the buyer is repricing rather than substituting — because Rubin's ~10× tokens/MW means token cost still falls while our price rises. The margin waterfall flows toward the constrained layer: us.
Falsifier: NVIDIA gross margin guided down ≥200bp with memory cited as cause AND an SK volume/ASP concession in the same window.
AMBER
Circular financing now quantified — bear row 12 extension $164.5B in guarantees
NVIDIA disclosed $164.5B of land/power/shell guarantees + AI-cloud agreements — $105B backstopping OpenAI at SB Energy's Ohio campus (4.25GW + 3.75GW option). Coverage is real (~$310B FCF capacity ≈ 2× obligations, phased from FY29) and the market is already discounting ACIE for it. But this is the transmission mechanism if the cycle turns: vendor-financed demand unwinds first, and it unwinds through orders — ours included. Now extended: NVIDIA vendor financing likely underwrites SpaceX’s NVIDIA-exclusive 10GW build (SemiAnalysis, 7 Aug) — the mechanism scales with the boom. The offset: inference economics are independently quantified at >$100B/GW/yr revenue vs ~$12B/GW/yr cost (60–85% inference gross margins; DeepSeek leak: 10-month GPU payback) — vendor-financed buyers are cash-generative from month one at current token prices. Token-price trajectory is therefore the tripwire that matters most. Real-vs-paper check (SemiAnalysis 3 Sep): the OpenAI/NVIDIA "8GW" Ohio campus groundbreaking is not construction — land and permits are still unsettled. Not a cancelled order; a reminder that GW on paper convert to memory orders only when shells and power exist.
Tripwires (extends row 12): guarantees >1× forward FCF · a neocloud default that triggers a guarantee · ACIE receivables/DSO stretching two consecutive quarters.
AMBER
8-hi HBM4 mix rising in H2 2026 thermals / yield / supply
Volume tailwind, ASP-mix headwind. Watch blended HBM ASP at Q3, not just bit shipments.
Falsifier of the worry: blended HBM ASP still rises QoQ despite the 8-hi shift → close item.
Reconciliation — corrections owned, gaps closed
Verified against the uploaded live files (current to 22 Aug). Two of my earlier flags were wrong; the real gaps are now patched.
My corrections (2): (1) "Price refs ₩2.215–2.33M stale" — wrong: those are the resistance ladder technical levels; the live anchor was ₩1.730M all along. (2) "July ₩283/450/610T model stale" — wrong: the live chain is ₩97/359/633/1,102T with clean EPS to ₩753K, already post-Patel-trim; this page now matches it exactly. Both errors came from working off stale knowledge-base snapshots instead of the files — your never-silently-patch rule caught them before they touched the site.
THE DISRUPTION REGISTER · could any chip or memory development cut memory demand in the next few years? · 4 Sep 2026
Short answer: nothing in silicon reduces memory demand. Every candidate below either shifts where the memory sits, changes the form factor it ships in, or moves the value split between stack, base die and package — and SK hynix supplies every one of those forms. The physics that would be needed for a real killer — a non-DRAM memory with DRAM-like latency and cost at frontier-model capacity — does not exist at scale this decade: SRAM costs well over ten times the silicon area per bit and cannot stack; the emerging non-volatile memories trade latency or endurance for density. The genuine 2028+ watch is HBM value capture (who earns the packaging and bandwidth premium), not bits.
| CANDIDATE | WHAT IT DOES | WHAT IT DOESN’T | STATUS · SK EXPOSURE |
|---|
| SRAM-first inference (Cerebras, Groq → NVIDIA LPX) | Fast decode from on-chip SRAM; less HBM per decode token | Can’t hold frontier weights or KV caches (tens of GB per die vs terabytes needed); prefill and training stay on HBM. The casualty was CPX/GDDR7, not HBM. | Shipping, niche · bear branch 2–5% already · LPX pools LPDDR — ours |
| Near-memory / 3D DRAM-on-logic (d-Matrix Raptor, Qualcomm HBC, PIM) | Bonds compute to DRAM; higher bandwidth per bit, ~6× lower interface energy | Still DRAM — bits made by the same three fabs; 32GB/card today vs 192–288GB HBM4; claims modelled | Silicon 2026, volume 2028+ · HBC: SK + Samsung confirmed collaborators · value-capture watch |
| High Bandwidth Flash (SanDisk–SK hynix standard) | NAND stacked HBM-style for read-mostly weights; far more capacity per stack | Can’t serve KV caches or training; complements HBM in inference tiers rather than replacing it | Sampling 2027–28 · SK is co-developer and owns the NAND — substitution flows to our other leg |
| Custom HBM / base-die shift (NVHBM, Feynman "die-stacking custom HBM") | Customer designs the base die and spec; memory makers build to it | Doesn’t reduce stacks; may move base-die value to NVIDIA/TSMC | 2027–28 · SK co-develops with NVIDIA · watch margin, not volume |
| Algorithmic efficiency (MoE sparsity, FP4/FP8, KV-cache compression, distillation) | Fewer bits per token — the only candidate that truly lowers memory per unit of work | Token volume grows faster than efficiency (Jevons): 18× tokens by 2030, Dell’s $95B backlog, Broadcom tripling. Concrete instance: Google’s TurboQuant cuts KV-cache memory ~5–6× — and Google still ships 288GB of HBM on every TPU 8i. Efficiency has so far raised hardware consumption | Continuous · bear row: token prices falling faster than costs — the tripwire that matters |
| Memory pooling / optics (CXL, NVLink Fusion, SK’s optical memory fabric) | Shares memory across processors; less stranded capacity | Historically raises addressable memory per job; SK publishes the fabric roadmap itself | 2028+ · ours (and Lumentum/Coherent’s) |
| Edge / on-device inference (phones, PCs, robots) | Moves some inference off the data centre | Runs on LPDDR and NAND — DRAM demand relocates, it doesn’t shrink; robot fleets are trained in data centres first | Growing · LPDDR5X/SOCAMM — ours |
| Chinese substitution (CXMT HBM3E pilot, YMTC) | Displaces Korean memory in Chinese sockets; price pressure on older generations | EUV-limited; 1–2 generations behind; no Rubin/HBM4E displacement | 2027–28 China sockets · branch 7% · monitored |
| New non-DRAM memory (MRAM, RRAM, FeRAM, photonic/holographic) | Would be the real killer if it matched DRAM latency, cost and density | None does; embedded niches only; the research sits inside Samsung, SK and Micron anyway | Not this decade · none |
What would change this table: a non-DRAM memory demonstrated at frontier-model capacity · token volume growth falling below efficiency gains for two consecutive quarters · a hyperscaler deploying near-memory silicon at scale with a non-big-3 DRAM source. None observed.
Real gaps, now closed in this patch set: forecast.html calibration was on Q2 consensus ₩83.0T → now Q2 actual ₩79.32T (a ~5% miss, honestly labelled) · comparison.html carried Q1 as latest quarter → now Q2 · the entire 26–27 Aug wave (NVDA print, FY28 guide, capex $1.3T, NVHBM, AWS 2M GPUs, LPX) was absent from every page → now on skhynix (two GREEN cards, verdict 8.2→8.4), index (plain-words big picture), forecast (demand anchors), comparison (demand row), flows (input refresh) and here. Net-cash discipline kept: ₩69.4T printed, not ₩100T. Path unified (27 Aug), trim reversed (28 Aug): the Patel −6% haircut was first propagated for consistency, then reversed as a misapplication: Patel’s compression warning targets 30-58× names — his "everything at 2-3×" endpoint is our entry multiple — and his exact scenario already sat in the engine as the largest bear branch (10% weight), so the central haircut double-counted it; his self-flagged rate guess has also faded (10Y 4.74→4.66%). One path site-wide: ₩5.5 → 8.0 → 8.4 → 7.9 → 8.5M. Both decisions in the audit trail.